PIC16F636-I/P【PDF 33/74 页】IC MCU FLASH 2KX14 14DIP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3889

29页 30页 31页 32页 [33页]34页 35页 36页 37页

Micrel, Inc.

KSZ8841-PMQL

October 2007

M9999-100407-1.5

MAC DMA Receive Start Command Register (MDRSC Offset 0x000C)

This register is written by the CPU when there are frame data in receive buffer to be processed.

The following table shows the register bit fields.

Bit

Default \

Read/

Write

Description

31 - 0

0x00000000

WRSC Receive Start Command

When written with any value, the Receive DMA checks for descriptors

to be acquired. If no descriptor is available, the receive process returns

to suspended state and wait for the next receive restart command. If

descriptors are available, the receive process resumes. This bit is self-

clearing.

Transmit Descriptor List Base Address Register (TDLB Offset 0x0010)

This register is used for Transmit descriptor list base address register. The register is used to point to the start of the

appropriate descriptor list. Writing to this register is permitted only when its respective process is in the stopped state.

When stopped, the register must be written before the respective START command is given.

Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8841-PMQL behavior is unpredictable when the lists are not word-

aligned.

The following table shows the register bit fields.

Bit

Default

Read/

Write

Description

31 - 0

0x00000000

WSTL Start of Transmit List

Note: Write can only occur when the transmit process stopped.

Receive Descriptor List Base Address Register (RDLB Offset 0x0014)

This register is used for Receive descriptor list base address register. The register is used to point to the start of the

appropriate descriptor list. Writing to this register is permitted only when its respective process is in the stopped state.

When stopped, the register must be written before the respective START command is given.

Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8841-PMQL behavior is unpredictable when the lists are not word-

aligned.

The following table shows the register bit fields.

Bit

Default

Read/

Write

Description

31 - 0

0x00000000

WSRL Start of Receive List

Note: Write can only occur when the transmit process stopped.

MAC Multicast Table 0 Register (MTR0 Offset 0x0020)

The 64 bit multicast table is used for group address filtering. The value is defined as the six most significant bits of the

CRC of the DA. The two most significant bits select the register to be used, while the other determines the bit within the

Bit

Default

Read/

Write

Description

31-0

0x00000000

MTR0 Multicast Table 0

When appropriate bit is set, the packet received with DA matches the

CRC hashing function is received without being filtered.

Note: when receive all (RXRA) or receive multicast (RXRM) bit is set in

the RXCR then all multicast addresses are received regardless of the

multicast table value.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式